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PTN3360B
Enhanced performance HDMI/DVI level shifter
Rev. 02 -- 8 October 2009 Product data sheet
1. General description
The PTN3360B is a high-speed level shifter device which converts four lanes of low-swing AC-coupled differential input signals to DVI v1.0 and HDMI v1.3a compliant open-drain current-steering differential output signals, up to 2.5 Gbit/s per lane. Each of these lanes provides a level-shifting differential buffer to translate from low-swing AC-coupled differential signaling on the source side, to TMDS-type DC-coupled differential current-mode signaling terminated into 50 to 3.3 V on the sink side. Additionally, the PTN3360B provides a single-ended active buffer for voltage translation of the HPD signal from 5 V on the sink side to 3.3 V on the source side and provides a channel for level shifting of the DDC channel (consisting of a clock and a data line) between 3.3 V source-side and 5 V sink-side. The DDC channel is implemented using pass-gate technology providing level shifting as well as disablement (isolation between source and sink) of the clock and data lines. The low-swing AC-coupled differential input signals to the PTN3360B typically come from a display source with multi-mode I/O, which supports multiple display standards, e.g., DisplayPort, HDMI and DVI. While the input differential signals are configured to carry DVI or HDMI coded data, they do not comply with the electrical requirements of the DVI v1.0 or HDMI v1.3a specification. By using PTN3360B, chip set vendors are able to implement such reconfigurable I/Os on multi-mode display source devices, allowing the support of multiple display standards while keeping the number of chip set I/O pins low. See Figure 1. The PTN3360B main high-speed differential lanes feature low-swing self-biasing differential inputs which are compliant to the electrical specifications of DisplayPort Standard v1.1 and/or PCI Express Standard v1.1, and open-drain current-steering differential outputs compliant to DVI v1.0 and HDMI v1.3a electrical specifications. The I2C-bus channel level-translates the DDC signals between 3.3 V (source) and 5.0 V (sink). The PTN3360B is a fully featured HDMI as well as DVI level shifter. It is functionally equivalent to PTN3300A but provides higher speed performance and higher ESD robustness. The PTN3360B is also equivalent to PTN3360A with the exception that PTN3360B provides non-inverting level shifting on the HPD channel. PTN3360B is powered from a single 3.3 V power supply consuming a small amount of power (120 mW typ.) and is offered in a 48-terminal HVQFN48 package.
NXP Semiconductors
PTN3360B
Enhanced performance HDMI/DVI level shifter
MULTI-MODE DISPLAY SOURCE OE_N reconfigurable I/Os PCIe PHY ELECTRICAL TMDS coded data PCIe output buffer TX FF TX TMDS coded data PCIe output buffer TX FF TX TMDS coded data PCIe output buffer TX FF TX TMDS clock pattern PCIe output buffer TX FF TX AC-coupled differential pair clock CLOCK LANE OUT_D1+ OUT_D1- IN_D1+ IN_D1- AC-coupled differential pair TMDS data DATA LANE IN_D2+ IN_D2- OUT_D2+ OUT_D2- AC-coupled differential pair TMDS data IN_D3+ DATA LANE IN_D3- OUT_D3+ OUT_D3- AC-coupled differential pair TMDS data IN_D4+ DATA LANE IN_D4- OUT_D4+ OUT_D4-
PTN3360B
0 V to 3.3 V
HPD_SOURCE_N
HPD_SINK
0 V to 5 V
3.3 V 3.3 V
DDC_EN (0 V to 3.3 V) 5V
SCL_SOURCE 3.3 V DDC I/O (I2C-bus) CONFIGURATION SDA_SOURCE
SCL_SINK 5V
SDA_SINK
002aae267
Remark: TMDS clock and data lanes can be assigned arbitrarily and interchangeably to D[4:1].
Fig 1.
Typical application system diagram
PTN3360B_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 8 October 2009
DVI CONNECTOR 2 of 22
NXP Semiconductors
PTN3360B
Enhanced performance HDMI/DVI level shifter
2. Features
2.1 High-speed TMDS level shifting
I Converts four lanes of low-swing AC-coupled differential input signals to DVI v1.0 and HDMI v1.3a compliant open-drain current-steering differential output signals I TMDS level shifting operation up to 2.5 Gbit/s per lane (250 MHz character clock) I Integrated 50 termination resistors for self-biasing differential inputs I Back-current safe outputs to disallow current when device power is off and monitor is on I Disable feature to turn off TMDS inputs and outputs and to enter low-power state
2.2 DDC level shifting
I Integrated DDC level shifting (3.3 V source to 5 V sink side) I 0 Hz to 400 kHz I2C-bus clock frequency I Back-power safe sink-side terminals to disallow backdrive current when power is off or when DDC is not enabled
2.3 HPD level shifting
I HPD non-inverting level shift from 5 V on the sink side to 3.3 V on the source side, or from 0 V on the sink side to 0 V on the source side I Integrated 200 k pull-down resistor on HPD sink input guarantees `input LOW' when no display is plugged in I Back-power safe design on HPD_SINK to disallow backdrive current when power is off
2.4 General
I I I I I Power supply 3.3 V 10 % ESD resilience to 8 kV HBM, 500 V CDM Power-saving modes (using output enable) Back-current-safe design on all sink-side main link, DDC and HPD terminals Transparent operation: no re-timing or software configuration required
3. Ordering information
Table 1. Ordering information Package Name PTN3360BBS HVQFN48 Description Version plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; SOT619-1 body 7 x 7 x 0.85 mm Type number
PTN3360B_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 8 October 2009
3 of 22
NXP Semiconductors
PTN3360B
Enhanced performance HDMI/DVI level shifter
4. Functional diagram
OE_N input bias enable
50 50
PTN3360B
OUT_D4+ OUT_D4-
IN_D4+ IN_D4- input bias enable
50 50
enable
OUT_D3+ OUT_D3-
IN_D3+ IN_D3- input bias enable
50 50
enable
OUT_D2+ OUT_D2-
IN_D2+ IN_D2- input bias enable
50 50
enable
OUT_D1+ OUT_D1-
IN_D1+ IN_D1- enable
HPD level shifter HPD_SOURCE (0 V to 3.3 V)
200 k
HPD_SINK (0 V to 5 V)
DDC_EN (0 V to 3.3 V) SCL_SOURCE
DDC level shifter SCL_SINK
SDA_SOURCE
002aae268
SDA_SINK
Fig 2.
Functional diagram of PTN3360B
PTN3360B_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 8 October 2009
4 of 22
NXP Semiconductors
PTN3360B
Enhanced performance HDMI/DVI level shifter
5. Pinning information
5.1 Pinning
48 IN_D4+ 46 VDD 45 IN_D3+ 42 IN_D2+ 40 VDD 39 IN_D1+ 47 IN_D4- 44 IN_D3- 41 IN_D2- 38 IN_D1-
43 GND
terminal 1 index area GND VDD n.c. n.c. GND REXT HPD_SOURCE SDA_SOURCE SCL_SOURCE 1 2 3 4 5 6 7 8 9
37 GND 36 GND 35 n.c. 34 n.c. 33 VDD 32 DDC_EN 31 GND 30 HPD_SINK 29 SDA_SINK 28 SCL_SINK 27 GND 26 VDD 25 OE_N GND 24
002aae269
PTN3360BBS
n.c. 10 VDD 11 GND 12 OUT_D4+ 13 OUT_D4- 14 VDD 15 OUT_D3+ 16 OUT_D3- 17 GND 18 OUT_D2+ 19 OUT_D2- 20 VDD 21 OUT_D1+ 22 OUT_D1- 23
Transparent top view
HVQFN48 package supply ground is connected to both GND pins and exposed center pad. GND pins must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the PCB in the thermal pad region.
Fig 3.
Pin configuration for HVQFN48
PTN3360B_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 8 October 2009
5 of 22
NXP Semiconductors
PTN3360B
Enhanced performance HDMI/DVI level shifter
5.2 Pin description
Table 2. Symbol OE_N Pin description Pin 25 Type Description
OE_N, IN_Dx and OUT_Dx signals 3.3 V low-voltage Output Enable and power saving function for high-speed differential CMOS single-ended level shifter path. input When OE_N = HIGH: IN_Dx termination = high-impedance OUT_Dx outputs = high-impedance; zero output current When OE_N = LOW: IN_Dx termination = 50 OUT_Dx outputs = active IN_D4+ 48 Self-biasing differential input Self-biasing differential input Self-biasing differential input Self-biasing differential input Self-biasing differential input Self-biasing differential input Self-biasing differential input Self-biasing differential input TMDS differential output TMDS differential output TMDS differential output TMDS differential output TMDS differential output TMDS differential output Low-swing differential input from display source with PCI Express electrical signalling. IN_D4+ makes a differential pair with IN_D4-. The input to this pin must be AC coupled externally. Low-swing differential input from display source with PCI Express electrical signalling. IN_D4- makes a differential pair with IN_D4+. The input to this pin must be AC coupled externally. Low-swing differential input from display source with PCI Express electrical signalling. IN_D3+ makes a differential pair with IN_D3-. The input to this pin must be AC coupled externally. Low-swing differential input from display source with PCI Express electrical signalling. IN_D3- makes a differential pair with IN_D3+. The input to this pin must be AC coupled externally. Low-swing differential input from display source with PCI Express electrical signalling. IN_D2+ makes a differential pair with IN_D2-. The input to this pin must be AC coupled externally. Low-swing differential input from display source with PCI Express electrical signalling. IN_D2- makes a differential pair with IN_D2+. The input to this pin must be AC coupled externally. Low-swing differential input from display source with PCI Express electrical signalling. IN_D1+ makes a differential pair with IN_D1-. The input to this pin must be AC coupled externally. Low-swing differential input from display source with PCI Express electrical signalling. IN_D1- makes a differential pair with IN_D1+. The input to this pin must be AC coupled externally. HDMI compliant TMDS output. OUT_D4+ makes a differential pair with OUT_D4-. OUT_D4+ is in phase with IN_D4+. HDMI compliant TMDS output. OUT_D4- makes a differential pair with OUT_D4+. OUT_D4- is in phase with IN_D4-. HDMI compliant TMDS output. OUT_D3+ makes a differential pair with OUT_D3-. OUT_D3+ is in phase with IN_D3+. HDMI compliant TMDS output. OUT_D3- makes a differential pair with OUT_D3+. OUT_D3- is in phase with IN_D3-. HDMI compliant TMDS output. OUT_D2+ makes a differential pair with OUT_D2-. OUT_D2+ is in phase with IN_D2+. HDMI compliant TMDS output. OUT_D2- makes a differential pair with OUT_D2+. OUT_D2- is in phase with IN_D2-.
IN_D4-
47
IN_D3+
45
IN_D3-
44
IN_D2+
42
IN_D2-
41
IN_D1+
39
IN_D1-
38
OUT_D4+ OUT_D4- OUT_D3+ OUT_D3- OUT_D2+ OUT_D2-
13 14 16 17 19 20
PTN3360B_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 8 October 2009
6 of 22
NXP Semiconductors
PTN3360B
Enhanced performance HDMI/DVI level shifter
Table 2. Symbol OUT_D1+ OUT_D1-
Pin description ...continued Pin 22 23 Type TMDS differential output TMDS differential output 5 V CMOS single-ended input Description HDMI compliant TMDS output. OUT_D1+ makes a differential pair with OUT_D1-. OUT_D1+ is in phase with IN_D1+. HDMI compliant TMDS output. OUT_D1- makes a differential pair with OUT_D1+. OUT_D1- is in phase with IN_D1-. 0 V to 5 V (nominal) input signal. This signal comes from the DVI or HDMI sink. A HIGH value indicates that the sink is connected; a LOW value indicates that the sink is disconnected. HPD_SINK is pulled down by an integrated 200 k pull-down resistor. 0 V to 3.3 V (nominal) output signal. This is level-shifted non-inverted version of the HPD_SINK signal. 3.3 V source-side DDC clock I/O. Pulled up by external termination to 3.3 V. 3.3 V source-side DDC data I/O. Pulled up by external termination to 3.3 V. 5 V sink-side DDC clock I/O. Pulled up by external termination to 5 V. 5 V sink-side DDC data I/O. Pulled up by external termination to 5 V. Enables the DDC buffer and level shifter. When DDC_EN = LOW, buffer/level shifter is disabled. When DDC_EN = HIGH, buffer and level shifter are enabled.
HPD and DDC signals HPD_SINK 30
HPD_SOURCE SCL_SOURCE SDA_SOURCE SCL_SINK SDA_SINK DDC_EN
7 9 8 28 29 32
3.3 V CMOS single-ended output single-ended 3.3 V open-drain DDC I/O single-ended 3.3 V open-drain DDC I/O single-ended 5 V open-drain DDC I/O single-ended 5 V open-drain DDC I/O 3.3 V CMOS input
Supply and ground VDD 2, 11, 15, 3.3 V DC supply 21, 26, 33, 40, 46 ground 1, 5, 12, 18, 24, 27, 31, 36, 37, 43 6 analog I/O Supply ground. All GND pins must be connected to ground for proper operation. Supply voltage; 3.3 V 10 %.
VCC GND[1]
Feature control signals REXT Current sense port used to provide an accurate current reference for the differential outputs OUT_Dx. For best output voltage swing accuracy, use of a 10 k resistor (1 % tolerance) from this terminal to GND is recommended. May also be left open-circuit or tied to either VDD or GND. See Section 6.2 for details. Not connected. May be left open-circuit or tied to GND or VDD either directly or via a resistor.
Miscellaneous n.c. 3, 4, 10, 34, 35 no connection to the die
[1]
HVQFN48 package supply ground is connected to both GND pins and exposed center pad. GND pins must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the PCB in the thermal pad region.
PTN3360B_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 8 October 2009
7 of 22
NXP Semiconductors
PTN3360B
Enhanced performance HDMI/DVI level shifter
6. Functional description
Refer to Figure 2 "Functional diagram of PTN3360B". The PTN3360B level shifts four lanes of low-swing AC-coupled differential input signals to DVI and HDMI compliant open-drain current-steering differential output signals, up to 2.5 Gbit/s per lane. It has integrated 50 termination resistors for AC-coupled differential input signals. An enable signal OE_N can be used to turn off the TMDS inputs and outputs, thereby minimizing power consumption. The TMDS outputs, HPD_SINK input and DDC_SINK I/Os are back-power safe to disallow current flow from a powered sink while the PTN3360B is unpowered. The PTN3360B's DDC channel provides passive level shifting, allowing 3.3 V source-side termination and 5 V sink-side termination. The PTN3360B offers back-power safe sink-side I/Os to disallow backdrive current from the DDC clock and data lines when power is off or when DDC is not enabled. An enable signal DCC_EN enables the DDC level shifter block. The PTN3360B also provides voltage translation for the Hot Plug Detect (HPD) signal from 0 V to 5 V on the sink side, non-inverting and level-shifting to 0 V/3.3 V on the source side. The PTN3360B does not re-time any data. It contains no state machines. No inputs or outputs of the device are latched or clocked. Because the PTN3360B acts as a transparent level shifter, no reset is required.
6.1 Enable and disable features
PTN3360B offers different ways to enable or disable functionality, using the Output Enable (OE_N) and DDC Enable (DDC_EN) inputs. Whenever the PTN3360B is disabled, the device will be in Standby mode and power consumption will be minimal; otherwise the PTN3360B will be in Active mode and power consumption will be nominal. These two inputs each affect the operation of PTN3360B differently: OE_N affects only the TMDS channels, and DDC_EN affects only the DDC channel. HPD_SINK does not affect either of the channels. The following sections and truth table describe their detailed operation.
6.1.1 Hot plug detect
The HPD channel of PTN3360B functions as a level-shifting buffer to pass the HPD logic signal from the display sink device (via input HPD_SINK) on to the display source device (via output HPD_SOURCE). The output logic state of HPD_SOURCE output always follows the logic state of input HPD_SINK, regardless of whether the device is in Active or Standby mode.
PTN3360B_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 8 October 2009
8 of 22
NXP Semiconductors
PTN3360B
Enhanced performance HDMI/DVI level shifter
6.1.2 Output Enable function (OE_N)
When input OE_N is asserted (active LOW), the IN_Dx and OUT_Dx signals are fully functional. Input termination resistors are enabled and the internal bias circuits are turned on. When OE_N is de-asserted (inactive HIGH), the OUT_Dx outputs are in a high-impedance state and drive zero output current. The IN_Dx input buffers are disabled and IN_Dx termination is disabled. Power consumption is minimized. Remark: Note that OE_N has no influence on the HPD_SINK input, HPD_SOURCE output, or the SCL and SDA level shifters. OE_N only affects the high-speed TMDS channel.
6.1.3 DDC channel enable function (DDC_EN)
The DDC_EN pin is active HIGH and can be used to isolate a badly behaved slave. When DDC_EN is LOW, the DDC channel is turned off. The DDC_EN input should never change state during an I2C-bus operation. Note that disabling DDC_EN during a bus operation will hang the bus, while enabling DDC_EN during bus traffic would corrupt the I2C-bus operation. Hence, DDC_EN should only be toggled while the bus is idle. (See I2C-bus specification).
PTN3360B_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 8 October 2009
9 of 22
NXP Semiconductors
PTN3360B
Enhanced performance HDMI/DVI level shifter
6.1.4 Enable/disable truth table
Table 3. Inputs HPD_SINK OE_N
[1] [2]
HPD_SINK, OE_N and DDC_EN enabling truth table Channels DDC_EN IN_Dx LOW OUT_Dx[3] DDC[4] high-impedance HPD_SOURCE[5] LOW Active; DDC disabled Active; DDC enabled Mode
LOW
LOW
50 termination enabled to VRX(bias) 50 termination enabled to VRX(bias)
LOW
LOW
HIGH
SDA_SINK connected to SDA_SOURCE and SCL_SINK connected to SCL_SOURCE high-impedance SDA_SINK connected to SDA_SOURCE and SCL_SINK connected to SCL_SOURCE high-impedance
LOW
LOW LOW
HIGH HIGH
LOW HIGH
high-impedance high-impedance
high-impedance; zero output current high-impedance; zero output current
LOW LOW
Standby Standby; DDC enabled
HIGH
LOW
LOW
50 termination enabled to VRX(bias) 50 termination enabled to VRX(bias)
HIGH
Active; DDC disabled Active; DDC enabled
HIGH
LOW
HIGH
SDA_SINK connected to SDA_SOURCE and SCL_SINK connected to SCL_SOURCE high-impedance SDA_SINK connected to SDA_SOURCE and SCL_SINK connected to SCL_SOURCE
HIGH
HIGH HIGH
HIGH HIGH
LOW HIGH
high-impedance high-impedance
high-impedance; zero output current high-impedance; zero output current
HIGH HIGH
Standby Standby; DDC enabled
[1] [2] [3] [4] [5]
A HIGH level on input OE_N disables only the TMDS channels. A LOW level on input DDC_EN disables only the DDC channel. OUT_Dx channels `enabled' means outputs OUT_Dx toggling in accordance with IN_Dx differential input voltage switching. DDC channel `enabled' means SDA_SINK is connected to SDA_SOURCE and SCL_SINK is connected to SCL_SOURCE. The HPD_SOURCE output logic state always follows the HPD_SINK input logic state.
PTN3360B_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 8 October 2009
10 of 22
NXP Semiconductors
PTN3360B
Enhanced performance HDMI/DVI level shifter
6.2 Analog current reference
The REXT pin (pin 6) is an analog current sense port used to provide an accurate current reference for the differential outputs OUT_Dx. For best output voltage swing accuracy, use of a 10 k resistor (1 % tolerance) connected between this terminal and GND is recommended. If an external 10 k 1 % resistor is not used, this pin can be left open-circuit, or connected to GND or VDD, either directly (0 ) or using pull-up or pull-down resistors of value less than 10 k. In any of these cases, the output will function normally but at reduced accuracy over voltage and temperature of the following parameters: output levels (VOL), differential output voltage swing, and rise and fall time accuracy.
6.3 Backdrive current protection
The PTN3360B is designed for backdrive prevention on all sink-side TMDS outputs, sink-side DDC I/Os and the HPD_SINK input. This supports user scenarios where the display is connected and powered, but the PTN3360B is unpowered. In these cases, the PTN3360B will sink no more than a negligible amount of leakage current, and will block the display (sink) termination network from driving the power supply of the PTN3360B or that of the inactive DVI or HDMI source.
PTN3360B_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 8 October 2009
11 of 22
NXP Semiconductors
PTN3360B
Enhanced performance HDMI/DVI level shifter
7. Limiting values
Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD VI Tstg VESD Parameter supply voltage input voltage storage temperature electrostatic discharge voltage HBM CDM
[1] [2]
Conditions 3.3 V CMOS inputs 5.0 V CMOS inputs
Min -0.3 -0.3 -0.3 -65 -
Max +4.6 VDD + 0.5 6.0 +150 8000 500
Unit V V V C V V
[1] [2]
Human Body Model: ANSI/EOS/ESD-S5.1-1994, standard for ESD sensitivity testing, Human Body Model Component level; Electrostatic Discharge Association, Rome, NY, USA. Charged-Device Model: ANSI/EOS/ESD-S5.3-1-1999, standard for ESD sensitivity testing, Charged-Device Model - Component level; Electrostatic Discharge Association, Rome, NY, USA.
8. Recommended operating conditions
Table 5. Symbol VDD VI VI(AV) Rref(ext) Tamb
[1] [2]
Recommended operating conditions Parameter supply voltage input voltage 3.3 V CMOS inputs 5.0 V CMOS inputs average input voltage IN_Dn+, IN_Dn- inputs external reference resistance[2] connected between pin REXT (pin 6) and GND
[1]
Conditions
Min 3.0 0 0 -40
Typ 3.3 0 10 1 % -
Max 3.6 3.6 5.5 +85
Unit V V V V k C
ambient temperature operating in free air
Input signals to these pins must be AC-coupled. Operation without external reference resistor is possible but will result in reduced output voltage swing accuracy. For details, see Section 6.2.
8.1 Current consumption
Table 6. Symbol IDD Current consumption Parameter supply current Conditions OE_N = 0; Active mode OE_N = 1 and DDC_EN = 0; Standby mode Min 10 Typ 35 0.8 Max 50 1.5 Unit mA mA
PTN3360B_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 8 October 2009
12 of 22
NXP Semiconductors
PTN3360B
Enhanced performance HDMI/DVI level shifter
9. Characteristics
9.1 Differential inputs
Table 7. Symbol UI VRX_DIFFp-p TRX_EYE Vi(cm)M(AC) ZRX_DC VRX(bias) ZI(se) Differential input characteristics for IN_Dx signals Parameter unit interval[1] minimum eye width at IN_Dx input pair includes all frequencies above 30 kHz
[4]
Conditions
[2] [3]
Min 360 0.175 0.8 40
[5]
Typ 50 1.2 -
Max 4000 1.200 100 60 1.4 -
Unit ps V UI mV V k
differential input peak-to-peak voltage receiver eye time peak common-mode input voltage (AC) DC input impedance bias receiver voltage single-ended input impedance inputs in high-impedance state
1.0 100
[6]
[1] [2] [3] [4] [5] [6]
UI (unit interval) = tbit (bit time). UI is determined by the display mode. Nominal bit rate ranges from 250 Mbit/s to 2.5 Gbit/s per lane. Nominal UI at 2.5 Gbit/s = 400 ps. 360 ps = 400 ps - 10 %. VRX_DIFFp-p = 2 x |VRX_D+ - VRX_D-|. Applies to IN_Dx signals. Vi(cm)M(AC) = |VRX_D+ + VRX_D-| / 2 - VRX(cm). VRX(cm) = DC (avg) of |VRX_D+ + VRX_D-| / 2. Intended to limit power-up stress on chip set's PCIe output buffers. Differential inputs will switch to a high-impedance state when OE_N is HIGH.
PTN3360B_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 8 October 2009
13 of 22
NXP Semiconductors
PTN3360B
Enhanced performance HDMI/DVI level shifter
9.2 Differential outputs
The level shifter's differential outputs are designed to meet HDMI version 1.3 and DVI version 1.0 specifications.
Table 8. Symbol VOH(se) VOL(se) VO(se) Differential output characteristics for OUT_Dx signals Parameter single-ended HIGH-level output voltage single-ended LOW-level output voltage single-ended output voltage variation logic 1 and logic 0 state applied respectively to differential inputs IN_Dn; Rref(ext) connected; see Table 5 single-ended 20 % to 80 % 80 % to 20 % intra-pair inter-pair tjit
[1] [2] [3] [4] [5] [6] [7]
[4] [4] [5] [6] [7]
Conditions
[1]
Min
Typ
Max
Unit
VTT - 0.01 VTT
VTT + 0.01 V
[2]
VTT - 0.60 VTT - 0.50 VTT - 0.40 V 400 500 600 mV
[3]
IOZ tr tf tsk
OFF-state output current rise time fall time skew time jitter time
75 75 -
-
10 160 160 10 250 7.4
A ps ps ps ps ps
jitter contribution
VTT is the DC termination voltage in the HDMI or DVI sink. VTT is nominally 3.3 V. The open-drain output pulls down from VTT. Swing down from TMDS termination voltage (3.3 V 10 %). Maximum rise/fall time at 2.5 Gbit/s = 400 ps. 360 ps = 400 ps - 10 %. This differential skew budget is in addition to the skew presented between IN_D+ and IN_D- paired input pins. This lane-to-lane skew budget is in addition to skew between differential input pairs. Jitter budget for differential signals as they pass through the level shifter.
9.3 HPD_SINK input, HPD_SOURCE output
Table 9. Symbol VIH VIL ILI VOH VOL tPD tt Rpd
[1] [2] [3] [4] [5]
HPD characteristics Parameter HIGH-level input voltage LOW-level input voltage input leakage current HIGH-level output voltage LOW-level output voltage propagation delay transition time pull-down resistance Conditions HPD_SINK HPD_SINK HPD_SINK HPD_SOURCE HPD_SOURCE from HPD_SINK to HPD_SOURCE; 50 % to 50 % HPD_SOURCE rise/fall; 10 % to 90 % HPD_SINK input pull-down resistor
[3] [2] [1]
Min 2.0 0 2.5 0 1 100
Typ 5.0 200
Max 5.3 0.8 10 VDD 0.2 200 20 300
Unit V V A V V ns ns k
[4] [5]
Low-speed input changes state on cable plug/unplug. Measured with HPD_SINK at VIH maximum and VIL minimum. Time from HPD_SINK changing state to HPD_SOURCE changing state. Includes HPD_SOURCE rise/fall time. Time required to transition from VOH to VOL or from VOL to VOH. Guarantees HPD_SINK is LOW when no display is plugged in.
(c) NXP B.V. 2009. All rights reserved.
PTN3360B_2
Product data sheet
Rev. 02 -- 8 October 2009
14 of 22
NXP Semiconductors
PTN3360B
Enhanced performance HDMI/DVI level shifter
9.4 OE_N, DDC_EN inputs
Table 10. Symbol VIH VIL ILI
[1]
OE_N, DDC_EN and DDET input characteristics Parameter HIGH-level input voltage LOW-level input voltage input leakage current OE_N pin
[1]
Conditions
Min 2.0 -
Typ -
Max 0.8 10
Unit V V A
Measured with input at VIH maximum and VIL minimum.
9.5 DDC characteristics
Table 11. Symbol fclk DDC characteristics Parameter clock frequency Conditions SCL_SOURCE, SDA_SOURCE, SCL_SINK, SDA_SINK pass gate in ON state; IO = 15 mA; VO = 0.4 V source side; VI = 3.3 V; IO = -100 A sink side; VI = 5.0 V; IO = -100 A Cio ILI Cio input/output capacitance input leakage current input/output capacitance VI = 3.3 V source side; 0 V < VI < 3.3 V sink side; 0 V < VI < 5.0 V VI = 3.3 V OFF state (DDC_EN = LOW) -10 -10 1 +10 +10 5 A A pF Min Typ Max 400 Unit kHz
ON state (DDC_EN = HIGH) RON VO(sw) ON resistance switch output voltage 1.7 1.7 7 2.1 2.1 5 30 2.5 2.5 10 V V pF
PTN3360B_2
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Product data sheet
Rev. 02 -- 8 October 2009
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PTN3360B
Enhanced performance HDMI/DVI level shifter
10. Package outline
HVQFN48: plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; body 7 x 7 x 0.85 mm
SOT619-1
D
B
A
terminal 1 index area A E A1 c
detail X
e1 e 13 L 12 25 e
1/2 e
C b 24 vMCAB wMC y1 C y
Eh
1/2 e
e2
1 terminal 1 index area 48 Dh 0 DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 7.1 6.9 Dh 5.25 4.95 E (1) 7.1 6.9 Eh 5.25 4.95 e 0.5 37
36
X 2.5 scale e1 5.5 e2 5.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1 5 mm
Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT619-1 REFERENCES IEC --JEDEC MO-220 JEITA --EUROPEAN PROJECTION ISSUE DATE 01-08-08 02-10-18
Fig 4.
PTN3360B_2
Package outline SOT619-1 (HVQFN48)
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 8 October 2009
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NXP Semiconductors
PTN3360B
Enhanced performance HDMI/DVI level shifter
11. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
11.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
11.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering
11.3 Wave soldering
Key characteristics in wave soldering are:
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities
PTN3360B_2 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 8 October 2009
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NXP Semiconductors
PTN3360B
Enhanced performance HDMI/DVI level shifter
11.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 5) than a SnPb process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 12 and 13
Table 12. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 13. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 5.
PTN3360B_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 8 October 2009
18 of 22
NXP Semiconductors
PTN3360B
Enhanced performance HDMI/DVI level shifter
temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 5.
Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
12. Abbreviations
Table 14. Acronym CDM DDC DVI ESD HBM HDMI HPD I2C-bus I/O TMDS Abbreviations Description Charged-Device Model Data Display Channel Digital Visual Interface ElectroStatic Discharge Human Body Model High-Definition Multimedia Interface Hot Plug Detect Inter-IC bus Input/Output Transition Minimized Differential Signaling
PTN3360B_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 8 October 2009
19 of 22
NXP Semiconductors
PTN3360B
Enhanced performance HDMI/DVI level shifter
13. Revision history
Table 15. Revision history Release date 20091008 Data sheet status Product data sheet Change notice Supersedes PTN3360B_1 Document ID PTN3360B_2 Modifications:
*
Section 6 "Functional description": - 3rd paragraph: 1st sentence re-written; deleted 2nd and 3rd sentences. - 5th paragraph, 2nd sentence: deleted phrase "except for the DDC/I2C-bus block"
* *
PTN3360B_1
Table 7 "Differential input characteristics for IN_Dx signals", Table note [6]: changed from "... when OE_N is LOW." to "... when OE_N is HIGH." Table 8 "Differential output characteristics for OUT_Dx signals", Table note [7]: deleted second sentence Product data sheet -
20090504
PTN3360B_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 8 October 2009
20 of 22
NXP Semiconductors
PTN3360B
Enhanced performance HDMI/DVI level shifter
14. Legal information
14.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
14.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
14.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk.
14.4 Licenses
Purchase of NXP ICs with HDMI technology Use of an NXP IC with HDMI technology in equipment that complies with the HDMI standard requires a license from HDMI Licensing LLC, 1060 E. Arques Avenue Suite 100, Sunnyvale CA 94085, USA, e-mail: admin@hdmi.org.
14.5 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
15. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
PTN3360B_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 8 October 2009
21 of 22
NXP Semiconductors
PTN3360B
Enhanced performance HDMI/DVI level shifter
16. Contents
1 2 2.1 2.2 2.3 2.4 3 4 5 5.1 5.2 6 6.1 6.1.1 6.1.2 6.1.3 6.1.4 6.2 6.3 7 8 8.1 9 9.1 9.2 9.3 9.4 9.5 10 11 11.1 11.2 11.3 11.4 12 13 14 14.1 14.2 14.3 14.4 14.5 15 16 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 High-speed TMDS level shifting . . . . . . . . . . . . 3 DDC level shifting . . . . . . . . . . . . . . . . . . . . . . . 3 HPD level shifting . . . . . . . . . . . . . . . . . . . . . . . 3 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 4 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 Functional description . . . . . . . . . . . . . . . . . . . 8 Enable and disable features . . . . . . . . . . . . . . . 8 Hot plug detect . . . . . . . . . . . . . . . . . . . . . . . . . 8 Output Enable function (OE_N) . . . . . . . . . . . . 9 DDC channel enable function (DDC_EN). . . . . 9 Enable/disable truth table . . . . . . . . . . . . . . . . 10 Analog current reference . . . . . . . . . . . . . . . . 11 Backdrive current protection . . . . . . . . . . . . . . 11 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 12 Recommended operating conditions. . . . . . . 12 Current consumption . . . . . . . . . . . . . . . . . . . 12 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 13 Differential inputs . . . . . . . . . . . . . . . . . . . . . . 13 Differential outputs . . . . . . . . . . . . . . . . . . . . . 14 HPD_SINK input, HPD_SOURCE output . . . . 14 OE_N, DDC_EN inputs. . . . . . . . . . . . . . . . . . 15 DDC characteristics . . . . . . . . . . . . . . . . . . . . 15 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16 Soldering of SMD packages . . . . . . . . . . . . . . 17 Introduction to soldering . . . . . . . . . . . . . . . . . 17 Wave and reflow soldering . . . . . . . . . . . . . . . 17 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 17 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 18 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 20 Legal information. . . . . . . . . . . . . . . . . . . . . . . 21 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 21 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Contact information. . . . . . . . . . . . . . . . . . . . . 21 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 8 October 2009 Document identifier: PTN3360B_2

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